What Spintronics Tells You About Future Information Processing
A large power required to store and process information hinders making our society greener. Semiconductor community has been exploring new technology, physics and materials included, to change this. Spintronics appears to have partially fulfilled the task, because it has opened a pathway towards low power CMOS VLSI through integration of nonvolatile memory based on magnetic tunnel junction (MTJ); MTJs feature high-speed and low-voltage operation below the standard supply voltage, large endurance, the use of relatively conventional materials compatible with CMOS back-end process including annealing conditions, and prospect of scaling far beyond current generation of device size (below 3 nm demonstrated). With MTJs, one can design a circuit that turns off blocks not in use to save stand-by power, which occupies a large portion of power consumption. Proof-of-concept demonstrations on standard 300 mm CMOS VLSI have been reported. I will summarize in my talk what spintronics has made possible over the years and what remains a challenge.
Hideo Ohno, currently President of Tohoku University, received B. S., M. S. and Ph.D. from the University of Tokyo in 1977, 1979 and 1982, respectively. He reported first InAlAs/InGaAs FET when he was a visiting graduate student at Cornell University in 1980 and then worked on MBE and MOVPE of III-V heterostructures as well as insulator/III-V interfaces during his time at Hokkaido University as lecturer and later associate professor at Hokkaido University since 1982. He synthesized a magnetic version of III-V compound, (In,Mn)As, during his stay at the IBM T. J. Watson Research Center as a visiting scientist from 1988 to 1990. Since he joined Tohoku University in 1994 as professor, he has worked on (Ga,Mn)As, a prototypical ferromagnetic semiconductor, demonstrated electric-field control of ferromagnetism in (In,Mn)As, developing currently de facto standard perpendicular CoFeB/MgO magnetic tunnel junction (MTJ), scaling those MTJs down below 3 nm, and integration of MTJs to prototype low-power MTJ-CMOS integrated circuits on 300 mm wafers. He has published 595 papers in the fields of spintronics and semiconductor science and technology with citation of over 52,000 (h-index 89). He has led the Funding Program for World-leading Innovative R&D on Science and Technology (FIRST), “Research and Development of Ultra-low Power Spintronics-based VLSIs” from 2010 to 2014. Ohno received the IBM Japan Science Award (1998), the IUPAP Magnetism Prize (2003), the Japan Academy Prize (2005), the 2005 Agilent Technologies Europhysics Prize (2005), the IEEE Magnetics Society Distinguished Lecturer for 2009 (2008), the Thomson Reuters Citation Laureate (2011), the JSAP Outstanding Achievement Award (2012), the IEEE David Sarnoff Award (2012), the JSAP Compound Semiconductor Electronics Achievement Award (2015), the Leo Esaki Prize (2016), the C&C Prize (2016), the MEXT Commendation for Science and Technology (2017) and the ISCS Welker Award (2019). He is a fellow of the Institute of Physics (IOP), the Japan Society of Applied Physics (JSAP), the American Physical Society (APS), and the Institute of Electrical and Electronics Engineers (IEEE).